Strained Silicon On Insulator Wafers

This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the smart cut tm technology can be used to obtain good quality tensile.

Strained silicon on insulator wafers.

Recently obtained sige free strained silicon on insulator by transferring strained si grown on relaxed sige buffer layers onto an oxide layer 3. Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard soi and or bulk like strained si layers. This process allows a larger window for thermal treatments. In combination with modified insulator layers also improvements of the electrical properties and optimized.

The thicknesses of the si sige stacks are ranging from 40 to 80 nm hence suited to partially depleted soi architectures while. For the wafer bonding which will be reported in this paper two final structures can be realized strained silicon on sgoi or strained silicon directly on insulator ssoi. The virtual substrate was bonded to an oxidized silicon wafer. For mosfets applications this new technology.

For both structures the silicon will be strained in tension by a so called virtual substrate i e. This gives rise to a highly nonequilibrium laser process and can vary significantly to that in normal bulk silicon substrate. The process starts with a virtual substrate having a thin strained silicon layer grown on top of a thick sige buffer. Si 0 83 ge 0.

A si 0 0 1 wafer containing relaxed sige today usually. Semiconductor wafer direct bonding combined with mechanical grinding of the donor wafer and chemical etching of the remaining silicon as well as the sige layer is an alternative to the hydrogen induced layer transfer hilt.